In copending application U.S. application Ser. No. 666,715, which is wholly assigned to the assignee of this application and which is hereby incorporated by reference, a trench memory cell structure is disclosed having a transistor and a storage capacitor formed inside a trench. The transistor is formed so that its channel is a portion of the substrate at the sidewall of the trench and occupies the upper portion of the trench (that is, the portion of the trench nearest the opening of the trench to the surface of the substrate). A polycrystalline silicon region formed in the lower portion of the trench serves as one plate of the capacitor. The substrate serves as the other plate. The plates are separated by an insulator, such as silicon dioxide, formed on the walls of the lower portion of the trench. Thus the substrate serves two distinct functions within the memory cell: as a channel region for the pass transistor and as a plate for the capacitor. However, these functions create competing demands for the doping characteristics of the substrate.
Ideally, the threshold voltage of the pass transistor is just high enough to insure that the transistor shuts off. This low threshold allows the pass transistor to be turned on by a signal on the word line in spite of the voltage drop across the long word lines of modern VLSI memory circuits. The threshold voltage of the pass transistor is directly dependent on the doping of the channel region. Thus the substrate should have a relatively low doping level.
On the other hand, the substrate needs a different doping level for optimal performance as one plate of the capacitor. Metal-oxide semiconductor(MOS) capacitors do not behave as a simple capacitor having two plates separated by a dielectric material. The stored charge alters the characteristics of the semiconductor material. For example, with a positive charge stored on the plate inside the trench and a P type doped substrate, at some level of positive charge enough negative charge carriers(electrons) are drawn to the surface of the silicon dioxide layer separating the two plates to invert the portion of the substrate adjacent to the silicon dioxide to N type. Thus a depletion barrier forms at the point of inversion from P to N type, stopping the flow of carriers across the depletion barrier, and creating, in essence, a second capacitor in series with the MOS capacitor. The resulting capacitance is determined by the equation: ##EQU1## from elementary circuit theory. It is desirable to maximize C.sub.TOT because the charge stored in a capacitor is proportional to the capacitance of the capacitor. It is desirable to store maximum charge on the capacitor because data represented by the larger capacitance is less susceptible to alteration by stray fields in the array, alpha particles and other sources of soft errors.
The depletion barrier acts as a dielectric for the second capacitor(C.sub.2). Therefore, decreasing the width of the depletion barrier increases C.sub.2 and thus C.sub.TOT. One way of reducing the width of the depletion layer is increasing the doping level of the substrate. This yields two benefits. First, because there are more free carriers in heavily doped material, the depletion layer will consume less material in response to the same level of inversion. Second, the higher the doping level of the substrate, the greater the field necessary to create inversion. Thus a substrate doped highly enough will not invert and the second capacitance will not arise at all.
The described embodiment in U.S. application Ser. No. 666,715 cited above addresses this conflict by forming the capacitor of the cell in a heavily doped substrate and the transistor portion of the cell in a lightly doped epitaxial layer formed on the surface of this substrate. However, this solution does not solve the problem because processing steps subsequent to the formation of the epitaxial layer and time cause some of the dopant atoms in the substrate to diffuse into the epitaxial layer as is shown in the doping profile in FIG. 1. This raises the doping level of the epitaxial layer and lowers the doping level of the substrate near the capacitor, both undesirable effects for the reasons discussed above.